Cache Coherency Before we dive into examples of the sorts of things we can do to lower variance, a brief detour into the internals of the modern CPUs we run our code on. One important aspect of modern CPUs is their caches. Each CPU core has private L1 and L2 caches to store both data and instructions. Because all CPU cores access the same physical address space, CPU cores coordinate access to the same address to ensure a consistent view of a given memory location. Cache coherence protocols help manage this consistent view (note this consistency is at a lower level than the sorts of protection provided by software locks, cache coherence protocols do not obviate the need for locks and care to avoid race conditions).
Software Performance: Cache Coherency And NUMA
Software Performance: Cache Coherency And…
Software Performance: Cache Coherency And NUMA
Cache Coherency Before we dive into examples of the sorts of things we can do to lower variance, a brief detour into the internals of the modern CPUs we run our code on. One important aspect of modern CPUs is their caches. Each CPU core has private L1 and L2 caches to store both data and instructions. Because all CPU cores access the same physical address space, CPU cores coordinate access to the same address to ensure a consistent view of a given memory location. Cache coherence protocols help manage this consistent view (note this consistency is at a lower level than the sorts of protection provided by software locks, cache coherence protocols do not obviate the need for locks and care to avoid race conditions).